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Huang, Y. Yeh, P. Deng, L. Chang ; Y. Chu, Y. Wu, J. Phys, , , Doi: Ma, B. Lin, B. Hsieh, Y. Wu , and J. AA, Lai, G. Yuji Zhao, Robert M.
Erin C. Kyle, Stephen W. Kaun, Peter G.
Renewable and Sustainable Energy 6, Express, 7, p Pal, M. Migliorato, C. Li, Y. Crutchley, I. In the present invention, AlN single crystal substrates are particularly preferred, and such substrates can be c-plane, m-plane, a-plane, or r-plane. An optoelectronic device built on a single crystal substrate will inherit the crystalline orientation of the substrate. This represents a larger bandgap than other nitrides such as GaN and InN, and it is therefore possible to alloy AlN with Ga or In in order to engineer the bandgap energy. Processes for preparing the single crystal AlN substrate can vary, but will typically involve physical vapor transport as opposed to chemical vapor deposition CVD techniques that involve chemical reaction of precursor molecules to form the desired material, meaning the preferred process involves physical transport of a vapor of the desired material i.
The deposition area typically includes a single crystal AlN seed material and the growth process is typically conducted in an inductively-heated reactor. Seeded PVT growth processes for growing single crystal AlN substrates suitable for use in the present invention are set forth, for example, in U.
Liu, Y. Cruz, Y. He has authored and coauthored more than peer-reviewed journal papers and holds patents. To include a comma in your tag, surround the tag with double quotes. Lett, 99 , , Crutchley, I.
Single crystal AlN substrates suitable for use in the present invention are commercially available from HexaTech, Inc. Crucibles useful in PVT crystal growth processes are set forth in U. High-quality substrates result in improved light output and a reduction in device failure for the light-emitting devices fabricated on the substrates. Evaluation of the quality of a single crystal substrate can be based on several measurements, including dislocation density.
Exemplary techniques for measuring defects in single crystal structures are known in the art, such as those techniques set forth, for example, in Dalmau et al. One method used to characterize the lattice distortion in single-crystal wafer substrates is to directly image the dislocation in the crystal by X-ray topography by using synchrotron radiation sources.
See e. Dislocation density can be observed by plan-view-imaging. The dislocation density is calculated by dividing the total number of dislocations by the area of the view field. As illustrated in FIG. After etching, the etched surface is observed and the number of etch pits is counted by electron microscopy or optical microscopy.
The dislocation density is then estimated by dividing the number of observed etched pits by the area of the view field. Imperfect surface preparation of the substrate can also increase the dislocation density of the resulting optoelectronic device. Accordingly, surface preparation techniques can be utilized to decrease the dislocation density.
In an embodiment of the present invention, the AlN substrate surface is prepared by grinding, followed by chemo-mechanical polishing to reduce residual surface roughness. AlN substrate treatment processes can also include reactive ion etching or wet etching using an alkaline solution. Details of the polishing process are not particularly limiting to the present invention.
Planarization processing by dry etching can also be used.
A very smooth and flat substrate surface, consisting of atomic steps, is desirable regardless of the surface preparation method used. High resolution X-ray diffraction HRXRD is another standard method used to characterize the lattice distortion in single crystal substrates. Bowen, B. Tanner, CRC Press , the entire disclosure of which is hereby incorporated by reference. A narrow peak suggests less lattice disorder in the crystal, which means low dislocation density. Specifically, the FWHM of X-ray RCs for the crystallographic plane of AlN substrates used in the present invention is preferably less than about arcsec, less than about arcsec, less than about 50 arcsec, or less than about 25 arcsec.
Exemplary ranges include about 1 to about arcsec, about 5 to about 50 arcsec, and about 10 to about 25 arcsec. The x-ray tube was in point focus set to 40 kV 45 mA. The double-axis configuration utilized a Ge 2 2 0 four-bounce monochromator and an open detector. The spot size of the X-ray beam is approximately 10 mm. As shown in FIGS. Semiconductor devices such as light-emitting devices comprise a multilayer structure formed on a base substrate.
In order to increase light emission efficiency, each layer requires high crystallinity with few dislocations and point defects. Generally, an LED comprises a multilayer structure including a substrate base as well as an active region between an n-type semiconductor layer electrically connected to an n-electrode and a p-type semiconductor layer electrically connected to a p-electrode. Achieving low defect densities throughout the active region is critical for the efficiency and lifetime of a nitride-based semiconductor device.
As discussed above, a high-quality substrate described herein is used to construct optoelectronic devices with low defect densities as well as desirable performance characteristics. The precise structure and method of preparation for the light-emitting devices of the invention can vary, but will typically involve epitaxial growth, mounting, and packaging processes known in the art. One of the advantages of using the high quality AlN substrates noted above to construct the light-emitting devices of the invention is the fact that less optimization of the light-emitting structure is required to obtain strong device performance.
Although the LED and LD devices of the invention can be simple homojunction or double heterostructure devices, multi-well active layer devices are preferred. The illustrated device includes an AlN substrate 15 as described above, with a typical thickness of about to about microns, with an overlying optional homoepitaxial AlN layer The presence of the homoepitaxial layer 20 , which is typically about to about nm in thickness, can improve the light emission efficiency of the multilayer structures subsequently fabricated on the homoepitaxial layer. In one embodiment, an optional graded buffer layer 25 having an exemplary thickness of about 0.
The buffer layer 25 may include or consist essentially of one or more n-type nitride semiconductor materials, e. In an embodiment, the buffer layer 25 has a composition approximately equal to that of the substrate. The buffer layer can improve the electrical and conductive characteristics of the bottom contact layer 30 discussed below. In another embodiment, the composition of the buffer layer 25 can be chosen to consist essentially of the same materials used for the active region 35 of the device.
A bottom contact layer 30 is also formed above the substrate The bottom contact layer 30 may include or consist essentially of Al x Ga 1-x N doped with at least one impurity, such as Si, and has a typical thickness of about 0. In an embodiment, the Al concentration in the bottom contact layer 30 is approximately equal to the Al concentration in the desired active region 35 of the device 10 described below. In a preferred embodiment, the bottom contact layer 30 is an n-type pseudomorphic layer, such as n-Al 0.
A quantum well is a potential well with only discrete energy values. Quantum wells are formed in semiconductors by having a one material sandwiched between two layers of a material with a wider band gap. Each of the at least one layers in the active region 35 can include or consist essentially of AlGaN.
eywaapps.dk/I/wp-content/realism/the-decoded-prophecies-of-nostradamus.php In a preferred embodiment, the quantum well structure 35 is a stack structure that combines multiple well layers with thicknesses from about 5 nm to about 50 nm, and barrier layers with larger band gap energy than the well layers. The band gap energy and thickness of the well layers and the barrier layers can be tailored to obtain desired optical emission properties.
Light emitting diodes (LEDs) are already used in traffic signals, signage Topics in Applied Physics III-Nitride Based Light Emitting Diodes and Applications. Topics in Applied Physics III-Nitride Based Light Emitting Diodes and Applications surrounding the development of III-Nitride LEDs and solid state lighting.
In a preferred embodiment, the emission wavelength of the optoelectronic devices is in the range from nm to nm e. In one embodiment, an optional electron blocking layer 40 or hole-blocking if the n-type contact is put on top of the device as the top contact layer can be formed above the active region The optional blocking layer 40 can include or consist essentially of Al x Ga 1-x N and can be doped with one or more impurities such as Mg.
A blocking layer 40 can, for example, have a thickness between about 2 nm and about 50 nm. A top contact layer 45 is formed above the active region The top contact layer is doped either n-type or p-type with a conductivity opposite that of the bottom contact layer In one embodiment, the top contact layer 45 is p-GaN with a typical thickness of about 50 mn to about nm. LDs incorporate additional layers which properly confine photons to create a resonant cavity.
In an edge-emitter LD, the resonant cavity is directed perpendicular to the layer growth direction and the semiconductor layer structure is cleaved or etched to create mirrors. In such an embodiment, the layers above and below the active region are modified to act as cladding layers to ensure that the emitted photons propagate perpendicular to layer growth direction without significant absorption. After fabricating the device layers, additional processes, such as etching to expose a given conductive layer and electrode formation steps to contact the conductive layer surface, are necessary to produce a functional light-emitting device.
The bottom contact layer 30 is electrically connected to a first electrode The top contact layer 45 is electrically connected to a second electrode In a preferred embodiment, the bottom contact layer 30 is an n-type semiconductor material electrically connected to a cathode 50 and the top contact layer 45 is a p-type semiconductor material electrically connected to an anode MOCVD processes are preferable in order to control the thickness of the device layers as well as the incorporation of dopants. Exemplary precursors for forming an n-type contact layer or a MQW structure include trimethylaluminum, trimethylgallium, ammonia, silane or tetraethylsilane and hydrogen gas as well as nitrogen as a carrier gas.